Mar 13, 2009 10:36 PM
Help with writing to external memory for a delay effect?
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HI all,
I took LukeD's old Delay code, which was posted in the old forum, and modified it based on the suggestions in the same thread. The delay code is shown in the reply to this post. The delay function is at the bottom of the text file (thanks LukeD).
The delay time, however, is very short (on the order of tens of miliseconds). I want to extend the delay time by using the external memory, but I am failing. I tried to use suggestions given in the old forum, but am still failing.
// ???
Can anyone help with modifying the code to extend the delay time (like to seconds instead of miliseconds)? If someone has done this in C, that would be equally as helpful (even more helpful).
// ???
My end goal is a function of the type: y(n) = x(n-Delay1) + x(n-Delay2)
where Delay1, Delay2 are controlled by knob1, knob2 with the range 0 to 1sec.
Thanks in advance.
///////////////////////////////
I have this example from the old forum, but my Assembly is too weak to get it to work. It may help someone else:
(if anyone knows the author, please note who it was. I don't have their name)
////////////////////////////////
Posted: Jan 19, 2009 8:24 AM
Hi,
I’ve just finished my first prototype. This one needed to access to the external memory. I performed this without using the DMA module. This code doesn’t appear in the documentation. So I thought it can be interesting if I give it to you.
This is how to perform a simple write in the 8bits external memory:
move #>$ABCDEF,a1 ;Move the data in the a1 register
move #>$200000,r0 ;Move the destination address to r0
move a1,y:(r0)+ ;Copy the lowest 8bits to the external data and increment r0
lsr #8,a1 ;logical shift right of 8bits
move a1,y:(r0)+
lsr #8,a1
move a1,y:(r0)
Of Course, to copy the 24bits information, you need three 8bits cells in your external memory.
To read the external memory,the code is similar:
move #>$200000,r0 ;Move the source address to r0
move y:(r0)+,b1 ;Copy the lowest 8bits and increment r0
move b1,x0 ;move the results in r0
move y:(r0)+,b1 ;Copy the other 8bits and increment r0
lsl #8,b1 ; logical shift left of 8bits
or x0,b1 ;add the information to x0(logical or)
move b1,x0 ;the result of the or was on b1
move y:(r0),b1
lsl #16,b1
or x0,b1
move b1,x0
//////////////////////////////
;The code is here:
page 132,60
include "..\Ioequ.inc"
include "..\vectors4.inc"
list
; History: modified from LukeD's Delay post on
; tonecore forum using forum suggestions
;
; ?: need help reading/writing external memory
; for a longer delay
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; Constants
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;BufferSize equ 1024 ; the buffer size
BufferSize equ 768 ; the buffer size
AccessSRAMWord0 equ $982245 ; 1 0 011 00 0 00100 0 100100 01 01
; DMA Control Register for channel 0
; bit(s)value description
; [23] = DE = 1 DMA Operation disabled (Trigger DMA transfer)
; [22] = DIE = 0 DMA Interrupt disabled
; [21:19] = DTM[2:0] = 011 triggered by DE, DE=0 after done
; [18:17] = DPR[1:0] = 00 priority level 0
; [16] = DCON = 0 Continuous mode disabled
; [15:11] = DRS[4:0] = 00100 Transfer done from channel 0
; [10] = D3D = 0 non 3-d mode
; [9:4] = DAM[5:0] = 100100 no update s/d
; [3:2] = DDS[1:0] = 01 Y memory destination
; [1:0] = DSS[1:0] = 01 Y memory source
AccessSRAMWord1 equ $982A45 ; 1 0 011 00 0 00101 0 100100 01 01
; DMA Control Register for channel 0
; bit(s)value description
; [23] = DE = 1 DMA Operation disabled (Trigger DMA transfer)
; [22] = DIE = 0 DMA Interrupt disabled
; [21:19] = DTM[2:0] = 011 triggered by DE, DE=0 after done
; [18:17] = DPR[1:0] = 00 priority level 0
; [16] = DCON = 0 Continuous mode disabled
; [15:11] = DRS[4:0] = 00101 Transfer done from channel 1
; [10] = D3D = 0 non 3-d mode
; [9:4] = DAM[5:0] = 100100 no update s/d
; [3:2] = DDS[1:0] = 01 Y memory destination
; [1:0] = DSS[1:0] = 01 Y memory source
;**************************************************************************
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; Variables
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org x:$000
;...Knob registers expect a value of 0x000000 thru 0x7FFFFF from the microcontroller
Knob_1 ds 1 ; 00h
Knob_2 ds 1 ; 01h
Knob_3 ds 1 ; 02h
Knob_4 ds 1 ; 03h
Knob_5 ds 1 ; 04h
Knob_6 ds 1 ; 05h
;...Switch registers expect a value of 0,1, or 2 from the microcontroller
Switch_1 ds 1 ; 06h
Switch_2 ds 1 ; 07h
;...FootSwitch registers expect a value of 0x000000 or 0x000001 from the microcontroller
FootSwitch_TopLayer ds 1 ; 08h
FootSwitch_BottomLayer ds 1 ; 09h
;...LED registers are read by the micro and should be set to 0x000000 or 0x000001 (off and on)
LED_Red ds 1 ; 0ah
LED_Green ds 1 ; 0bh
;...RX and TX registers
LeftRx ds 1 ; 0ch Left received sample
RightRx ds 1 ; 0dh Right received sample
LeftTx ds 1 ; 0eh Left sample to transmit
RightTx ds 1 ; 0fh Right sample to transmit
SHI_StateMachine ds 1 ; 10h current state of the serial host interface
HostCommand ds 1 ; 11h current SHI command
;...Debug registers
Debug_Write_to_DSP_1 ds 1 ; 12h recieves data from the ToneCoreGUI application
Debug_Write_to_DSP_2 ds 1 ; 13h recieves data from the ToneCoreGUI application
Debug_Write_to_DSP_3 ds 1 ; 14h recieves data from the ToneCoreGUI application
Debug_Write_to_DSP_4 ds 1 ; 15h recieves data from the ToneCoreGUI application
Debug_Read_from_DSP_1 ds 1 ; 16h send data to the ToneCoreGUI application
Debug_Read_from_DSP_2 ds 1 ; 17h send data to the ToneCoreGUI application
Debug_Read_from_DSP_3 ds 1 ; 18h send data to the ToneCoreGUI application
Debug_Read_from_DSP_4 ds 1 ; 19h send data to the ToneCoreGUI application
;...FootLatch says whether the simulated latch is up or down
;...FootLatchMem is compared to the current state of FootSwitch_BottomLayer to decide
; whether the simulated latch is up or down
FootLatch ds 1 ; 1Ah
FootLatchMem ds 1 ; 1Bh
LeftInput ds 1 ; 00h
LeftOutput ds 1
Depth ds 1
Delay ds 1
Feedback ds 1
org y:$000
Buffer dsm (BufferSize)
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; Macros
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HandleFootSwitch MACRO
;Handles the foot switch, turns on/off bypass if need be
;Use Bottom layer of FootSwitch to turn on/off analog bypass
;
; Uses b, x0, and x1
;
; take the momentary footswitch signal (pulse) and generate a latched (step) control signal
move x:FootSwitch_BottomLayer,b ; load unmodified footswitch input
move x:FootSwitch_BottomLayer,x1 ; load unmodified footswitch input
not b x:FootLatchMem,x0 ; not a (also, load the previous momentary signal into x0)
and x0,b x1,x:FootLatchMem ; x0 & a (also, store current momentary signal for next iteration)
move x:FootLatch,x0 ; load previous latched value
eor x0,b ; generate current latched (step) control signal
move b1,x:FootLatch ; store latched footswitch signal created from momentary footswitch
move x:FootLatch,b ; load latching footswitch signal
jclr #0,b,_ANALOG_BYPASS ; bit clear = bypass
movep #>$000008,x:M_PDRB ; bit 3 on = FX_ON Also Pre-Emph, Post-DeEmph Off, Direct Off
bset #0,x:LED_Green ; turn led on to indicate effect on
jmp _END_ANALOG_BYPASS
_ANALOG_BYPASS:
movep #>$000004,x:M_PDRB ; bit 2 on = DIRECT_ON, All else off
bclr #0,x:LED_Green ; turn led off to indicate effect off
_END_ANALOG_BYPASS:
ENDM
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; Code Start
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org p:$4E
START
ori #$03,mr ; mask interrupts
movep #$2D0063,X:M_PCTL ; Set PLL Control Register
; Fosc = 100 MHz = (100)(3 MHz)/3
bset #14,omr ; allow address attributes line to function independently
movep #>$000040,x:M_SAICR ; 4x4 Synchronous mode (use TX frame and bit clks)
movep #$FCC304,x:M_TCCR
;THCKD -1- HCKT is an output (bit 23)
;TFSD -1- FST is output (bit 22)
;TCKD -1- internal clock source drives SCKT (bit 21)
;THCKP -1- Transmitter High Freq Clock Polarity (bit 20)
;TFSP -1- negative FST polarity (bit 19)
;TCKP -1- data & FST clocked out on falling edge (bit 18)
;TFP -3- TFP3..0 = Divide by 4 (bits 17:14)
;TDC -1- 2 words per frame (bits 13:9)
;TPSR -1- Bypass Fixed /8 Prescaler (bit 8)
;TPM -4- TPM7-0 = Divide by 5 (bits 7:0)
movep #$FCC304,x:M_RCCR
;RHCKD -1- HCKR is an output Flag 2 (bit 23)
;RFSD -1- FSR is output Flag 1 (bit 22)
;RCKD -1- SCKR is output Flag 0 (bit 21)
;RHCKP -1- Pos. High Freq Clock Polarity (bit 20)
;RFSP -1- negative FSR polarity (bit 19)
;RCKP -1- data & FSR clocked in on falling edge (bit 18)
;RFP -3- RFP3..0 = Divide by 4 (bits 17:14)
;RDC -1- 2 words per frame (bit 13:9)
;RPSR -1- Bypass Fixed /8 Prescaler (bit 8)
;RPM -4- RPM7-0 = Divide by 5 (bits 7:0)
movep #$707d00,x:M_RCR
;RE --- RX0, RX1, RX2, RX3 disabled (bit3:0=0000)
;RSHFD -0- MSB shifted first (bit6=0)
;RWA -0- word left-aligned (bit7=0)
;RMOD -1- network mode (bit9:8=01)
;RSWS 1F- 32-bit slot length, 24-bit word length (bit14:10=11111)
;RFSL -0- word-length frame sync (bit15=0)
;RFSR -0- frame sync occurs 1 clock cycle earlier (bit16=1)
; reserved (bit18:17=00)
;RPR ?-0- transmit normally, not personal reset (bit19=0)
; RIE, REDIE, REIE enabled (bit23:20=0111)
;RLIE --- bit23 RLIE
;RIE --- bit22 RIE
;REDIE --- bit21 REDIE
;REIE --- bit20 REIE
movep #$027D80,x:M_TCR
;TE --- Start w/ TX0-TX5 disabled (bit5:0=000000)
;TSHFD -0- MSB shifted first (bit6=0)
;TWA -1- word left-aligned (bit7=0)
;TMOD -1- network mode (bit9:8=01)
;TSWS 1F- 32-bit slot length, 24-bit word length (bit14:10=11111)
;TFSL -0- word length frame sync (bit15=0)
;TFSR -0- frame sync occurs 1 clock cycle earlier (bit16=1)
;PADC -1- zero padding enabled (bit17=1)
; reserved (bit18)
;TRP ?-0- transmit normally, not personal reset (bit19=0)
; TLIE, TIE, TEIE disabled (bit23:20=0000)
;TLIE --- bit23 TLIE
;TIE --- bit22 TIE
;TEDIE --- bit21 TEDIE
;TEIE --- bit20 TEIE
movep #>$000000,x:M_PDRC ; Clear Port C data
movep #>$000BF8,x:M_PCRC ; Set appropriate Port C GPIO pins for ESAI .
movep #>$000C7E,x:M_PRRC ; Set pin direction of PORT C
;sdo0 sdo1 sdo2 sdo3 sdo4 sdo5 hckt fst sckt hckr fsr sckr
;ESAI GPO GPI GPI GPI ESAI ESAI ESAI ESAI GPO GPO NC
;DAC Data Inhibit IRQA Stereo/Mono A_In B_In ADC_Data 256FS_CLK0 FS_CLK 64FS_CLK Gain Switching Codec_Reset SS_Module
movep #>$000000,x:M_PCRB ; Set up Port B for output
movep #>$00000F,x:M_PRRB ; Set up Port B for output
movep #>$000008,x:M_PDRB ; bit 0 = In_EMPH
; bit 1 = OUT_DE_EMPH
; bit 2 = DIRECT_ON
; bit 3 = FX_ON
movep #>$000003,x:M_RSMA ; Enable first 2 time slots for receive.
movep #>$000000,x:M_RSMB ;
movep #>$000003,x:M_TSMA ; Enable first 2 time slots for transmit.
movep #>$000000,x:M_TSMB
movep #>$000000,x:M_TX0 ; zero out transmitter 0
;ENABLE ESAI
bset #0,x:M_RCR ; now enable RX0
bset #0,x:M_TCR ; now enable TX0
;...Setup Expansion Port A for SRAM...
movep #$2406B5,x:M_AAR0
; [23:12] = 0x240 Address used to assert chip select
; [11:8] = 0110 Number of address bits to compare = 6
; [7] = 1 Bit Packing Enabled
; [6] = 0 Address Mux Disabled
; [5] = 1 Y Space Enabled
; [4] = 1 X Space Enabled
; [3] = 0 P Space Disabled
; [2] = 1 Active High for Address Line
; [1:0] = 01 SRAM Mode
movep #$2003B1,x:M_AAR1
; [23:12] = 0x200 Address used to assert chip select
; [11:8] = 0011 Number of address bits to compare = 3
; [7] = 1 Bit Packing Enabled
; [6] = 0 Address Mux Disabled
; [5] = 1 Y Space Enabled
; [4] = 1 X Space Enabled
; [3] = 0 P Space Disabled
; [2] = 0 Active Low for Chip Select
; [1:0] = 01 SRAM Mode
;...Bus Control Register for SRAM...
movep #$0124A5,x:M_BCR ; 0001 0010 0100 0110 0011
;bus request hold off (bit23=0)
;bus lock hold off (bit22=0)
;bus state (bit21=0)
;default area wait states (bit20:16=00001)
;area 3 wait states (bit15:13=001)
;area 2 wait states (bit12:10=001)
;area 1 wait states (bit9:5=00011)
;area 0 wait states (bit4:0=00011)
;...Set up SHI (Serial Host Interface to the MCU)...
movep #>$003001,x:M_HCKR ; Turn Data/Clk Line Filter to max, wide spike tolerance (100ns glitch)
; CPHA=1, CPOL=0 : => same as reset/power-on.
movep #>$001189,x:M_HCSR ;
;...Initialize registers
move #>$000000,x0
move x0,r0
rep #26
move x0,x:(r0)+ ; clear start of x:mem
move #>$400000,x0 ; Intialize the knob registers
move x0,x:Knob_1
move x0,x:Knob_2
move x0,x:Knob_3
move x0,x:Knob_4
move x0,x:Knob_5
move x0,x:Knob_6
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; Setup
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Setup:
;move #500,y0
move #768,y0
move y0,x:Delay
move #>Buffer,r0
move #>Buffer,r1
move #>$00bfff,m3
move #>(BufferSize-1),m0
move #>(BufferSize-1),m1
move #>(BufferSize-10),m2
move #>(BufferSize),y0
move #>$000000,x0
move #$00ffff,m5 ; Use r5 for the MCU parameter updates.
movep x0,x:M_HTX ; Assert HREQ* pin for the MCU.
;...Initialize Peripheral Interrupt Priority Register for Audio Interrupts and SHI.
movep #$000007,x:M_IPRP ; ESAI int's enabled and top Priority
; SHI int's enabled and lowest Priority.
andi #$FC,mr ;enable all interrupt levels
;clear scaling bits
movep #>$000002,x:M_PDRC ; Take CODEC out of power down mode.
;------------------------------------------------------------
; Main loop
;------------------------------------------------------------
nop
nop
dor forever,LOOP
wait
nop
nop
nop
LOOP
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; 4x4 Interrupt Service Routines
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;-----------------------------
; Host Interrupt
;-----------------------------
shi_receive
movep x:M_HRX,x:HostCommand ; Get word from 8031.
movep #000000,x:M_HTX ; Assert HREQ* pin for 8031.
btst #0,x:HostCommand ; $000001 = Write 1 DSP word to X:mem.
bcs DoWriteCommand ;
btst #3,x:HostCommand ; $000008 = Send word to the 8031.
bcs DoReadCommand ;
DoWriteCommand
jclr #M_HRNE,x:M_HCSR,* ; Wait for address.
movep x:M_HRX,r5 ; Store address to write to.
movep #>000000,x:M_HTX ; Assert HREQ* pin for 8031.
jclr #M_HRNE,x:M_HCSR,* ; Wait for data
movep x:M_HRX,x:(r5) ; Write data.
movep #000000,x:M_HTX ; Assert HREQ* pin for 8031.
rti
DoReadCommand
jclr #M_HRNE,x:M_HCSR,*
movep x:M_HRX,r5 ; Store Address to read from
movep #>000000,x:M_HTX
jclr #M_HRNE,x:M_HCSR,*
movep x:M_HRX,n5
movep x:(r5),x:<<M_HTX ; Send Data at specified address to the 8031
jclr #M_HRNE,x:M_HCSR,*
movep x:M_HRX,n5
movep #>000000,x:<<M_HTX
rti
;-----------------------------
; Receive Exception Interrupt
;-----------------------------
esai_rxe_isr ; ESAI RECEIVE ISR
bclr #7,x:M_SAISR ; Read SAISR to clear receive
; overrun error flag
bclr #14,x:M_SAISR ; Read SAISR to clear transmit
; underrun error flag
movep x:M_RX0,x:RightRx ;
movep x:RightTx,x:M_TX0 ;
rti
;-----------------------------
; Receive Interrupt
;-----------------------------
esai_rx_isr
movep x:M_RX0,x:RightRx
movep x:RightTx,x:M_TX0
rti
;-----------------------------
; Receive Even Slot Interrupt
;-----------------------------
esai_rxeven_isr
; Mono effect, so no right line
movep x:M_RX0,x:LeftRx
move x:LeftOutput,x0 ;
move x0,x:LeftTx ; Transmit the output from the last sample period.
movep x:LeftTx,x:M_TX0
move x:LeftRx,a ; receive left
move a,x:LeftInput ; Save Current LeftInput sample
;Note: r5 and n5 are currently reserved for Host Interrupts
move x:Knob_2,x0
move x0,x:Depth
move x:Knob_3,x0
move x0,x:Feedback
;move x:Knob_1,x0
;move x0,x:Delay
;Process LeftInput
;move #$7fff,x0 ; for the time being, ignore what is on knob 2 and just make the
;move x0,x:Depth ; the amplitude of the delayed sample = 1 times ($7fff = 0.999999) the amplitude of the current sample
;move #>500,x0 ; set the delay to decimal 500, note the force right symbol
;move x0,x:Delay
;
; Done with forcing the input variables to known constants
;
;move r0,r1 ; r0 and r1 now contain the read pointer
;move x:LeftInput,a ; a = x(n) = newest input sample
;move x:Delay,n1 ; load delay amount in samples
;move x:Depth,x0 ; x0 = Depth (value from knob 2, floating point from -1 to 1?)
;move x:(r1+n1),y0 ; y0 = x(n-N}, the sample from N samples ago
;move a,x:(r0)+ ; store the newest input sample x(n) into the history buffer, update write ptr
;mac x0,y0,a ; a = Depth*x(n-N) + x(n); a = current input sample + depth*the delayed sample
;move a,x:LeftOutput ; write the output, note by choosing a here it will round as appropriate
move x:LeftInput,a
move a,b
move x:Delay,n1
move r0,r1
move x:Depth,x0
move y:(r0),y0
mac x0,y0,a
move a,y0
move x:Feedback,x0
mac x0,y0,b
move b1,y:(r1+n1)
move a1,x:LeftOutput
;increase buffer index
lua (r0)+,r0
move r0,x:Debug_Read_from_DSP_2
HandleFootSwitch
rti
Hey, so I just updated the Flanger effect & uploaded the latest source code (sorry, comments are a bit bare in parts. I meant to fix that, but never got around to it). There's still a few bugs that appear when you use multiple voices, but the important part is that I use the external memory for the delay, so you can look at that to see how I do it. (I'm using the DMA module by the way)
Source: http://sites.google.com/site/lukedsfiles/tcddk/flanger.zip
Thanks you, sir. I'm going to look at it now.
Luke,
I stripped down your flanger code and made a delay using the external memory. Thanks so much! Your flanger works great. I recorded some sounds before chopping it up.
I was able to get a delay of 130ms using a BufferSize=10240, DelayLimit=102439, and MinDelayLimit=1. I calculated the delay it to be 260ms, but I'm only able to get 130ms (recorded and checked using SoundForge).
I got the max buffer size through experimentation.
Can you point me in a direction for maximizing the buffer size in order to maximize the delay length?
Thanks again.
Unfortunately, because of the way I wrap around the buffer (I use m0 and m1 to do wrap around addressing), the maximum buffer size (and therefore, the maximum delay) is pretty small, something like 30000 samples. By the way, the delay limit must be at most the buffer size.
If you read through the Family Manual, I think I remember seeing that there is some way to do wrapping in the DMA that allows larger sizes, but I never read how to do it. Sorry =/
I'd help you out more, but I have a lot of real life stuff at the moment. (Also, I already own a really nice delay pedal and don't have much reason to write one)
If I get some free time, I'll probably look into this. I'll let you know what I find, but it could be a few weeks before I get to it.
Alternatively, you could try setting m0 and m1 to 0, use direct addressing mode, and just see what happens. That will try to use the entire y space for your buffer so make sure you have nothing else stored in y space at all. I have no idea if that'd work or not though to be honest.
Luke,
Please check your PM's.
Thanks,
John
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